Product development efforts in flash memory devices have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times, reducing cell dimensions, and optimizing dielectric materials used in memory cells. One important dielectric material for fabrication of the flash memory device is an Oxide-Nitride-Oxide (ONO) stack. During programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO stack. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom oxide layer and become trapped and stored in the nitride layer.
The ONO stack can be utilized in memory cells capable of storing two independent bits in separate locations within the memory cell, such as Advanced Micro Devices' (AMD) MirrorBit™ memory cells, to achieve high-density flash memory devices. In a conventional two-bit memory cell, a right and a left bit can be stored in respective storage locations situated on the right and left sides of the conventional two-bit memory cell. The right and left bits are stored as electrical charges, which, as discussed above, are stored in the charge storage layer, i.e. the nitride layer, of the ONO stack in the conventional two-bit memory cell. However, in the conventional two-bit memory cell, the nitride layer is a continuous layer. As a result, electrical charge can travel between the separate storage locations in the conventional two-bit memory cell, which can cause remnant charge to form in the middle of the charge storage layer of the ONO stack and undesirably decrease the performance of the conventional two-bit memory cell. Also, remnant charge can cause an undesirable increase in cell erasure time, since remnant charge represents additional charge that must be removed during a cell erase cycle.
Additionally, a conventional two-bit memory cell that is situated on an edge of a memory cell array (“edge memory cell”) utilizes only one storage location and, consequently, does not suffer from the undesirable affects of remnant charge. However, in a conventional two-bit memory cell that is not situated on an edge of the memory cell array (“core memory cell”), electrical charge can travel between two storage locations within the cell, which can cause undesirable remnant charge to occur in the channel between the two storage locations. As a result, the threshold voltage of a conventional edge two-bit memory cell is different than the threshold voltage of a conventional core two-bit memory cell, which undesirably affects the overall performance of the conventional two-bit memory cell array.
Thus, there is a need in the art for a two-bit memory cell that achieves increased performance while preventing undesirable occurrence of remnant charge within the two-bit memory cell.